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Ordering number :EN *5684
CMOS LSI
LC74201E
Video CD Decoder
Preliminary Overview
The LC74201E is a CMOS LSI that reduces the signal processing functions required of a video CD decoder to a single chip. All that it takes to make a version 1 or version 2 video CD player is the addition of a CD digital signal processor, DRAM, an audio D/A converter, digital video encoder, and similar components.
Package Dimensions
unit: mm 3182-QFP-128E
[LC74201E]
Features
* Incorporation of virtually almost all the functionality required by a video CD player from the CD-ROM decoder through to the MPEG audio and video decoders in a single chip * Fully automatic playback with automatic decoding within the LSI in response to simple external commands and the MPEG bit stream * Special playback functions are activated by command inputs, and do not require signal processing by the host microcomputer * Support for two external DRAM configurations: 4 M bits (256k x 16 bits) or 4 M bits (256k x 16 bits) + 1 M bit (64k x 16 bits) * Support for a Track 1 DRAM user area (i.e., sector buffer) of up to 8 k bytes (4 M bits of external DRAM) or 22 k bytes (5 M bits of external DRAM) * Automatic synchronization of audio and video * Built-in high-speed decoder core that supports variablespeed video playback at up to quadruple speed. Audio support for normal and double-speed playback. * Internal registers that offer configuration settings for connecting to most commercially available CD digital signal processors and D/A converters * Compatible with version 2 of the video CD standard. Support for superimposition of closed caption data on the output signal as specified in the EIA608 standard * Support for Photo CD standard. (Base/4 and Base/16)
SANYO: QIP-128E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT) No. 5684-1/21
LC74201E Pin Assignment
No. 5684-2/21
LC74201E Pin Function 1. Power supply, test pin, unconnected pins
Pin No. 17 39 60 75 81 124 20 37 54 69 76 105 DVSS1 - - System power supply (connect to ground) DVDD1 - - System power supply (3-V power supply: 3.7 to 4.0 V) Symbol I/O Logic Function
29 114
DVDD2
-
-
Power supply for 5-V I/O pins (5-V power supply: 5.5 0.5 V)
33 112
DVSS2
-
-
Power supply for 5-V I/O pins (connect to ground)
65 67 125 127
AVSS AVDD CLKO TEST
- - Out In
- - Positive Positive
Power supply for VCO and PLL (connect to ground) Power supply for VCO and PLL (3-V power supply: 3.7 to 4.0 V) Power supply for VCO and PLL (connect to ground) Test mode control pin (normally kept at low level) Unconnected pins 34, 36, 40, 42, 53, 57, 64, 82, 83, 84 pins 85, 86, 97, 98, 108, 110, 126, 128 pins
NC
-
-
No. 5684-3/21
LC74201E 2. Clock pins
Pin No. 18 Symbol FSCO I/O Out Logic Positive Function Subcarrier clock output (frequency = 1/4 pixel clock frequency). Tristate output using DVDD2 (5-V) power supply. Pixel clock output (NTSC-4fsc, PAL-4fsc, or 13.5 MHz). Tristate output using DVDD1 (3-V) power supply.
19 55 56 58 56 59 61
PCKO XPALIN XPALOUT XNTIN XNTOUT CLKSEL
Out In Out In Out In
Positive -
Crystal oscillator connections for PAL-4fsc oscillation circuit (4fsc = 17.734475 MHz) - - Crystal oscillator connections for NTSC-4fsc oscillation circuit (4fsc = 14.31818 MHz) - Positive Clock selection control input. High: 54.0-MHz clock input from pin 62 (CLKIN); Low: clock from internal VCO oscillator. 54.0-MHz clock input (with built-in bias). When not used, connect to DVDD1 or DVSS1. Adjustment resistor connection for VCO oscillator circuit. PLL filter connection CD-DSP clock input (16.9344, 2.8224, or 2.1168 MHz)
62 63 66 68
CLKIN VCOR PLLFIL CDCK
In - - In
Positive - - Positive
3. Microcomputer interface
Pin No. 38 41 43 Symbol REST IRQ AS/DS (CE) I/O In Out In Logic Negative Negative Positive Function System reset input (Hysteresis input; built-in pull-up resistor). Interrupt request signal output (N-channel open-drain output). Parallel interface: Address/data select input (Low = address). Serial interface: Serial transfer enable signal input (High = enabled). Parallel interface: Strobe signal input for address input and data I/O. Serial interface: Serial transfer clock signal input. Parallel interface: Address/data I/O port P0 (LSB). Serial interface: ZPSerial data output (LSB-first input). Parallel interface: Address/data I/O port P1. Serial interface: Serial data input (LSB-first output).
44
STB (CL)
In
Positive
45
AD0 (DO)
I/O
Positive
46 47 48 49 50 51 52
AD1 (DI) AD2 AD3 AD4 AD5 AD6 AD7 (MBS)
I/O I/O I/O I/O I/O I/O I/O
Positive Positive Positive Positive Positive Positive Positive
Parallel interface address/data I/O ports. The interface mode is determined by the input levels at the AD4 to AD6 pins at the rising edge of the RESET pin input. * Serial interface: AD6:AD5:AD4 = 1:*:* (* = Don't care) * Parallel interface: AD6:AD5:AD4 = 0:1:0 AD7: Parallel interface address/data I/O port P7 (MSB).
Note: AD0 to AD7 use N-channel open-drain outputs.
No. 5684-4/21
LC74201E 4. CD interfaces
Pin No. 70 71 72 73 74 Symbol CDEMPH CDC2P CDSD CDBCK CDLRCK I/O In In In In In Logic Positive Positive Positive Positive Positive Emphasis input (hysteresis input) C2 error flag input (hysteresis input) Serial data input (hysteresis input) Serial data bit clock input (hysteresis input) Left/right clock input (hysteresis input) Function
5. Audio D/A converter interface
Pin No. 77 78 79 80 Symbol AULRCK AUEMPH AUDOUT AUBCO I/O Out Out Out Out Logic Positive Positive Positive Positive Audio data left/right clock output Audio emphasis flag output Audio data serial output Audio data bit clock output Function
Note:The four pins making up the audio D/A converter interface all use N-channel open-drain outputs.
6. Video interface
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21 22 23 24 Symbol BV0 (LSB) BV1 BV2 BV3 BV4 BV5 BV6 BV7 (MSB) GU0 (LSB) GU1 GU2 GU3 GU4 GU5 GU6 GU7 (MSB) RY0 (LSB) RY1 RY2 RY3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Logic Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Tristate output using DVDD1 (3-V) power supply. Tristate output using DVDD2 (5-V) power supply. Video signal outputs (R/Y signals). (Inputs only in test mode.) Tristate output using DVDD1 (3-V) power supply. Video signal outputs (G/U signals). (Inputs only in test mode.) Tristate output using DVDD2 (5-V) power supply. Video signal outputs (G/U signals). (Inputs only in test mode.) Tristate output using DVDD1 (3-V) power supply. Video signal outputs (B/V signals). (Inputs only in test mode.) Function Video signal outputs (B/V signals). (Inputs only in test mode.)
Continued on next page.
No. 5684-5/21
LC74201E
Continued from preceding page
Pin No. 25 26 27 28 30 31 Symbol RY4 RY5 RY6 RY7 (MSB) HSYNC CSYNC I/O I/O I/O I/O I/O Out Out Logic Positive Positive Positive Positive Negative Negative Tristate output using DVDD2 (5-V) power supply. Horizontal synchronization signal output. Tristate output using DVDD2 (5-V) power supply. Composite synchronization signal output. Tristate output using DVDD2 (5-V) power supply. Blanking signal output (horizontal and vertical blanking interval signal). Tristate output using DVDD2 (5-V) power supply. Video output enable signal input. High: Enable output. Data bus to DRAM. Function Video signal outputs (R/Y signals). (Inputs only in test mode.)
32
BLANK
Out
Positive
35 87 88 89 90 91 92 93 94 95 96 99 100 101 102 103 104
VOE DD15 (MSB) DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 (LSB)
In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive
Tristate output using DVDD2 (5-V) power supply. Row address strobe signal output to expansion 1-Mbit DRAM. Tristate output using DVDD2 (5-V) power supply.
106
RAS1
Out
Positive
107
RAS0
Out
Positive
7
109 111 113
WE CAS OE
Out Out Out
Positive Positive Positive
Write enable signal output to DRAM. Tristate output using DVDD2 (5-V) power supply. Column address strobe signal output to DRAM. Tristate output using DVDD2 (5-V) power supply. Output enable signal output to DRAM. Tristate output using DVDD2 (5-V) power supply.
Continued on next page.
No. 5684-6/21
LC74201E
Continued from preceding page
Pin No. 115 116 117 118 119 120 121 122 123 Symbol AA8 (MSB) AA7 AA6 AA5 AA4 AA3 AA2 AA1 AA0 (LSB) I/O Out Out Out Out Out Out Out Out Out Logic Positive Positive Positive Positive Positive Positive Positive Positive Positive Tristate output using DVDD2 (5-V) power supply. Address output to DRAM. Function
Block Diagram
No. 5684-7/21
LC74201E Block Descriptions 1. CD-ROM decoder This block takes the MPEG bit stream from the external CD digital signal processor and decodes it in accordance with the CD-ROM standard. * * * * The decoded data is automatically transferred to the next stage, the system decoder. Storing the decoded data in DRAM is also possible. The high-speed decoder core supports quadruple-speed playback. Internal registers offer settings for connecting to most commercially available CD digital signal processors. -- 32- or 24-slot -- LSB or MSB first -- Front- or rear-packing for data -- Rising or falling edge for bit clock
* The video CD's track 1 data can be stored in a user area set aside in the external DRAM. * An auto restart function stores the address of the last sector accessed before a pause so that playback can resume at the next sector when the pause ends. * The contents of the sector header and subheader are available from registers. 2. System decoder This block analyzes the MPEG bit stream, splits it into video and audio bit streams, and transfers these bit streams to the corresponding decoders. It calculates the decode start timing from the time stamp and the decoders' inherent delays and generates the necessary start signals to provide automatic synchronization of audio and video outputs. 3. CPU interface This interface allows the CPU to access the internal registers to set parameters controlling operation and to read out operational status. It may be configured as either an 8-bit parallel interface multiplexing data and addresses or as a 4-wire serial interface. 4. Audio decoder This block decodes the MPEG1 audio bit stream from the system decoder in accordance with the ISO11172-3 standard. * * * * * * The use of 24-bit internal precision yields high audio quality. The decoder supports all MPEG audio modes defined for layers 1 and 2 except the free format mode. Internal registers offer settings for connecting to most commercially available D/A converters. The block includes a cross attenuator compliant with the CD-i standard. The block supports readout of the frame header data. The block performs CRC checking. If there is an error, it automatically substitutes the preceding frame stored in DRAM. If there are continuous errors, it switches to muting.
Cross Attenuator
No. 5684-8/21
LC74201E 5. Video decoder This block decodes all layers (from the video sequence layer to the block layer plus the headers) from the MPEG1 video bit stream from the system decoder in accordance with the ISO11172-2 standard. * The decoding requires no external signal processing. The LSI internals handle everything automatically. All that is required from outside the chip are simple commands and the MPEG bit stream. * A PLL circuit permits synchronization of the system clock with the CD digital signal processor. Commands offer a choice of the following frequencies. -- 16.9344 MHz -- 2.8224 MHz -- 2.1168 MHz * The decoder supports the following image formats. -- 352 dots x 240 lines, 29.97 Hz (NTSC, PAL-60 Hz) -- 352 dots x 240 lines, 23.976 Hz (Film) -- 352 dots x 288 lines, 25.00 Hz (PAL) -- 704 dots x 480 lines, high-resolution still image (NTSC) -- 704 dots x 576 lines, high-resolution still image (PAL) * Built-in filters provide high image quality. -- Built-in sampling rate conversion filter for horizontal direction -- Built-in vertical filter * The decoder supports a variety of video output specifications. -- Support for NTSC (59.94 Hz) and PAL (50 Hz) monitors -- Built-in video timing generator -- Switching between interlaced and non-interlaced operation -- Built-in YUV-to-RGB conversion matrix with choice of 24-bit RGB, 24-bit YUV, and 16-bit YUV output -- Film-NTSC conversion -- Simple two-way conversion between NTSC or Film and PAL with built-in aspect ratio conversion -- Choice of pixel clocks: 13.5 MHz, 6.75 MHz, and 4 fsc * The decoder offers special playback functions. -- Special playback functions require no signal processing by the CPU. -- Such functions as double-, triple-, and quadruple-speed playback, still image playback, pause, slow, and singlestepping (one-cut play) are available with simple commands. -- The built-in multitile function offers the display of 4 or 16 small images on the screen with the display positions freely selectable and processing of up to two fields supported. -- The built-in wipe function supports wiping within a frame, display outside that frame, and changing the frame color. * The decoder includes bit buffer management functions. -- These monitor the bit buffer for errors and control the decoder to automatically adjust the amount of data in the bit buffer to maintain normal operation at all times. -- Depending on the state of the bit buffer, the decoder automatically skips or repeats images. Skipping gives precedence to B pictures. * The decoder includes frame buffer management functions. These provide all internal support for frame buffer mapping control (for the display, reconstruction frame,front frame, and rear frame) and the mapping control and setting accompanying mode changes between high-resolution still images and motion picture playback. * The decoder includes various fail-safe functions. * The decoder supports version 2 of the video CD standard. -- User data is accessible from outside the decoder. -- The decoder supports superimposition of closed caption data on the output RGB/YUV signal as specified in the EIA608 standard. * The decoder supports decoding of Photo CDs (using Base/4 and lower).
No. 5684-9/21
LC74201E 6. DRAM arbiter This block provides the interface to the external DRAM. In addition to the standard 4-M bit DRAM, there can also be a 1-M bit DRAM for supporting PAL high-resolution still image playback. If this additional DRAM is not available, the LSI trims the top and bottom 48 lines of the image and provides a function for vertically scrolling the display area in 16-line increments.
No. 5684-10/21
LC74201E Absolute Maximum Ratings
Parameter Symbol VDD1 Power supply voltage VDD2 VDD3 VIN1 DVDD1 pin DVDD2 pin AVDD pin BV0 to EV3, GU0 to GU3, RY0 to RY3, RESET, XPALIN, XNTIN, CLKIN, VCOR, PLLFIL, TEST pins VOE, AS/DS, STB, AD0 to AD7, CLKSEL Input voltage VIN2 CDCK, CDEMPH, CDC2P, CDSD, CDBCK, CDLRCK pins VIN3 BV4 to BV7, GU4 to GU7, RY4 to TY7, DD0 to DD15 pins BV0 to EV3, GU0 to GU3, RY0 to RY3, VOUT Output voltage VOUT VOUT Maximum current drain Operating temperature Storage temperature Pd max Topr Tstg PCK0, XPALOUT, XNTOUT, CLK0, AULRCK, AUEMPH, AUDOUT, AUBC0 pins IRQ, AD0 to AD 7, CAS pins BV4 to BV7, GU4 to GU7, RY4 to TY7, FSC0, HSYNC, CSYNC, BLANK, RAS0, RAS1, WE, OE, AA0 to AA8 pins Ta = 25C - -25 -40 500 +75 +125 mW C C DVSS2 - 0.3 DVSS2 + 0.3 V DVSS1 - 0.3 - V DVSS1 - 0.3 DVDD1 + 0.3 V DVSS2 - 0.3 DVSS2 + 0.3 V DVSS1 - 0.3 5.5 V DVSS1 - 0.3 DVDD1 + 0.3 V Conditions Ratings min DVSS1 - 0.3 DVSS2 - 0.3 AVSS - 0.3 max DVSS1 + 4.0 DVSS2 + 6.0 AVSS + 4.0 Unit V V V
Recommended Operating Conditions at Ta = -25C to +75C
Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VIH1 VIH2 VIH3 High-level input voltage VIH4 VIH5 VIL1 VIL2 Clock frequency Input amplitude FOSC1 FOSC2 VIN1 FIN1 FIN2 Clock duty fduty DVDD1 pin DVDD2 pin AVDD pin BV0 to BV3, GU0 to GU3,RY0 to RY3 pins RESET pin VOE, AD0 to AD7, CDCK, CLKSEL, TEST pins AS/DS, STB, CDEMPH, CDC2P, CDSD, CDBCK, CDLRCK pins BV4 to BV7, GU4 to GU7, RY4 to RY7, DD0 to DD15 pins BV0 to BV7, GU0 to GU7, RY0 to RY7, VOE, CDCK, AD0 to AD7, CLKSEL, TEST, DD0 to DD15 pins RESET, AS/DS, STB, CDEMPH, CDC2P,CDSD, CDBCK, CDLRCK pins XPALIN, XPALOUT pins (PAL) XNTIN, XNTOUT pins (NTSC) CLKIN pin (CLKSEL = high; FIN2 = 54 MHz) Command - 11hex; D1, D0 = 0,0 Input frequency CDCK pin Command - 11hex; D1, D0 = 0,1 Command - 11hex; D1, D0 = 1,0 CLKIN pin (CLKSEL = high) CLKIN, CDCK pins Conditions Ratings min 3.7 4.5 3.7 0.7VDD1 0.8VDD1 0.7VDD1 0.8VDD1 0.7VDD1 VSS1 - 0.3 VSS1 - 0.3 - - 1.0 - - - - 40 typ - 5.0 - - - - - max 4.0 5.5 4.0 VDD1 + 0.3 VDD1 + 0.3 5.5 5.5 Unit V V V V V V V
-
VDD2 + 0.3 0.3VDD1 0.2VDD1 - - VDD1 + 0.3 - - - - 60
V
Low-level input voltage
-
V
- 17.734475 14.31818 - 16.9344 2.1168 2.8224 54.000 -
V MHz MHz Vp-p MHz MHz MHz MHz %
No. 5684-11/21
LC74201E Electrical Characteristics at Ta = -25 to +75C, DVDD1 = AVDD = 3.7 V and DVDD2 = 5.0 V unless otherwise specified.
Parameter Symbol IIH1 IIH2 IIH3 High-level input current IIH4 IIH5 IIH6 IIL1 IIL2 IIL3 Low-level input current IIL4 IIL5 IIL6 Pull-up resistor RPU1 RPD1 Conditions AS/DS, STB, CDEMPH, CDC2P,CDSD, CDBCK, CDLRCK pins. Condition: VIN = 5.5 V VOE, CLKSEL, CDCK, TEST pins. Condition: VIN = 5.5 V RESET pin. Condition: VIN = DVDD1 CLKIN pin. (CLKSEL = low) Condition: VIN = DVDD1 VCOR, PLLFIL pins. (RESET = low) Condition: VIN = DVDD1 VCOR, PLLFIL pins. (RESET = low) Condition: VIN = DVDD1 AS/DS, STB, CDEMPH, CDC2P,CDSD, CDBCK, CDLRCK pins. Condition: VIN = DVSS1 VOE, CLKSEL, CDCK, TEST pins. Condition: VIN = DVSS1 RESET pin. Condition: VIN = DVSS1 CLKIN pin. (CLKSEL = low) Condition: VIN = DVSS1 VCOR, PLLFIL pins. (RESET = low) Condition: VIN = DVDD1 VCOR, PLLFIL pins. (RESET = low) Condition: VIN = DVDD1 RESET pin. Condition: DVDD1 = 3.7 V XPALIN pin. (NTSC mode) Condition: DVDD1 = 3.7 V XNTIN pin. (PAL mode) Condition: DVDD1 = 3.7 V DD0 to DD15 pins. (Standby mode) Condition: DVDD2 = 5.0 V Ratings min - typ - max 1 Unit A
- - -
- - -
1 1 1
A A A
-
-
1
A
-
-
1
A
-1
-
-
A
-1 -1 -1
- - -
- - -
A A A
-1
-
-
A
-1 - -
- 30 30
- - -
A k k
Pull-down resistor
RPD2
-
30
-
k
RPD3
100
-
-
k
Continued on next page.
No. 5684-12/21
LC74201E
Continued from preceding page.
Ratings min - typ 1 max -
Parameter
Symbol RBIAS1
Conditions XPALIN, XPALOUT, XNTIN, XNTOUT pins. Condition: DVDD1 = 3.7 V CLKIN pin. (CLKSEL = high) Condition: DVDD1 = 3.7 V BV0 to BV3, GU0 to GU3, RY0 to RY3, PCK0,
Unit M
Built-in feedback resistor RBIAS2
-
1
-
M
VOH1
AULRCK, AUEMPH, AUDOUT, AUBCO pins. Conditions: DVDD1 = 3.7 V, IOH = -1.0 mA CLK0 pin. Conditions: DVDD1 = 3.7 V, IOH = -1.0 mA BV4 to BV7, GU4 toGU7, RY4 toRY7, FSC0,
3.2
-
-
V
VOH2 High-level output voltage VOH3
3.5
-
-
V
HSYNC, CSYNC, BLANK, DD0 to DD15 RAS0, RAS1, WE, OE, AA0 to AA8 pins. Conditions: DVDD1 = 3.7 V, IOH = -1.0 mA
4.5
-
-
V
VOH4
XPALOUT, XNTOUT pins. Conditions: DVDD1 = 3.7 V, IOH = -0.1 mA BV0 to BV3, GU0 to GU3, RY0 to RY3, PCK0,
3.5
-
-
V
VOL1
AULRCK, AUEMPH, AUDOUT, AUBCO pins Conditions: DVDD1 = 3.7 V, IOL = 1.0 mA CLKO pin. Conditions: DVDD1 = 3.7 V, IOL = 1.0 mA BV4 to BV7, GU4 toGU7, RY4 toRY7, FSC0,
-
-
0.5
V
VOL2 Low-level output voltage VOL3
-
-
0.2
V
HSYNC, CSYNC, BLANK, DD0 to DD15 RAS0, RAS1, WE, OE, AA0 to AA8 pins. Conditions: DVDD2 = 5.0 V, IOL = 1.0 mA
-
-
0.5
V
VOL4 VOL5 VOL6 IOFF1 IOFF2 Output off leak current IOFF3
IRQ, AD0 to AD7 pins. Conditions: DVDD1 = 3.7 V, IOL = 1.0 mA CAS pin. Conditions: DVDD1 = 3.7 V, IOL = 1.0 mA XPALOUT, XNTOUT pins. Conditions: DVDD1 = 3.7 V, IOL = 0.1 mA BV0 to BV3, GU0 to GU3, RY0 to RY3, PCK0 pins. Condition: VOUT = DVDD1 or DVSS IRQ, AD0 to AD7, CAS pins Conditions: VOUT = 5.5 V or DVSS BV4 to BV7, GU4 to GU7, RY4 toRY7, FSC0, HSYNC, CSYNC, BLANK, DD0 to DD3 RAS0, WE, OE, AA0 to AA7 pins. Conditions: VOUT = DVDD2 or DVSS
-
-
0.5
V
-
-
0.2
V
-
-
0.2
V
-1
-
1
A
-1
-
1
A
-1
-
1
A
IDD1 Current drain during operation IDD2 IDD3
DVDD1 pin (All outputs open) AVDD pin (CLKSEL = low, VCO oscillating) DVDD2 pin (All outputs open)
- - -
(90) (15) (20)
mA mA mA
No. 5684-13/21
LC74201E Microcomputer Interface The microcomputer interface offers a choice of parallel or serial operation. The configuration is determined by the input levels at the AD4 to AD6 pins (pins 49 to 51) at the rising edge of the RESET pin (pin 38) input. * Parallel interface setting conditions [AD6, AD5, AD4] = [0, 1, 0]: Data read at rising edge of STB pin (pin 44) input. [AD6, AD5, AD4] = [0, 1, 1]: Data read at falling edge of STB pin (pin 44) input. [AD6, AD5, AD4] = [0, 0, 0]: Data read while STB pin (pin 44) input at high level. * Serial interface setting conditions [AD6, AD5, AD4] = [1, *, *] Notes: 1. Do not use any mode specifications other than the above. 2. A reset (RESET = low) configures the AD0 to AD7 pins (pins 45 to 52) for input. 3. The serial input mode fixes the AD2 to AD7 pins in input mode. Always treat them as input pins (by connecting them to either ground or DVDD1). If the interface is used for serial operation, the AD6 pin may be fixed at high level without any problems. 4. The RESET pin (pin 38) includes a built-in pul-up resistor. Do not apply a voltage higher than DVDD1. Timing Characteristics at Ta = +25C, DVDD1 = 3.7 V
Parameter Data setup time Data hold time Minimum reset pulse width Symbol TSDI0 THDI0 TWRST Conditions AD6 to AD4 RESET pin AD6 to AD4 RESET pin RESET pin Ratings min 180 180 180 max - - - Unit ns ns ns
No. 5684-14/21
LC74201E 1. Parallel interface The parallel interface uses the following two input pins and eight I/O pins. * AS/DS pin (pin 43: input): Address/data select input. low = address; high = data. * STB pin (pin 44: input): Strobe signal input for address input and data I/O. * AD0 pin (pin 45 : I/O): Address input and data I/O AD1 pin (pin 46 : I/O): Address input and data I/O AD2 pin (pin 47 : I/O): Address input and data I/O AD3 pin (pin 48 : I/O): Address input and data I/O AD4 pin (pin 49 : I/O): Address input and data I/O AD5 pin (pin 50 : I/O): Address input and data I/O AD6 pin (pin 51 : I/O): Address input and data I/O AD7 pin (pin 52 : I/O): Address input and data I/O Note: The address cannot be read. 1-1 Address and data transfer procedures The command address is assigned to the lowest seven bits of the address. The most significant bit (AD7) is used to specify write or read. The address can only be written. It cannot be read. * Writing data Drive the AS/DS pin (pin 43) at low level to specify address input. Specify the address in the lowest seven bits. Set the top bit to 0. Drive the STB pin (pin 44) at high level to cause the LSI to read the address. The parallel interface mode can be configured to read input using a choice of three different timings. -- Data read at rising edge of STB pin input. -- Data read at falling edge of STB pin input. -- Data read while STB pin input at high level.
Drive the AS/DS pin (pin 43) at high level to specify data I/O. Drive the STB pin (pin 44) at high level to cause the LSI to read the data.
No. 5684-15/21
LC74201E * Reading data Drive the AS/DS pin (pin 43) at low level to specify address input. Specify the address in the lowest seven bits. Set the top bit to 1.
Drive the AS/DS pin (pin 43) at high level to specify data I/O. Drive the STB pin (pin 44) at high level to cause the LSI to write the data.
1-2 Timing characteristics at Ta = +25C, DVDD1 = 3.7 V
Parameter Symbol twH1 twL1 tr1 tf1 tsDI1 tsDI2 Data hold time Single to word read/write time Data output propagation time thDI1 thDI2 tword tpLH1 tpHL1 Conditions STB pin high level pulse width STB pin low level pulse width STB pin STB pin AD7 to AD0 STB pin AS/DS STB pin STB AD0 to AD7 pin STB AS/DS pin AS/DS pin AD0 to AD7 data output high propagation time AD0 to AD7 data output low propagation time Ratings min 180 180 - - 25 25 25 25 200 - - max - - 50 50 - - - - - 150 55 Unit ns ns ns ns ns ns ns ns ns ns ns
Minimum input pulse width Strobe rising time Strobe falling time Data setup time
Note: AD0 to AD7 use N-channel open-drain outputs. The standard values for tpLH1 and tpHL1 are for an output load capacitance of 50 pF, an external pull to up resistor of 2.7 k, and an output level of 5.0 V.
No. 5684-16/21
LC74201E * Address/data write timing
* Data read timing
2. Serial interface The serial interface uses the following three input pins and one output pin. * * * * CE pin (pin 43: input): Serial transfer enable signal input CL pin (pin 44: input): Serial transfer clock signal input DO pin (pin 45: input): Serial transfer data output DI pin (pin 46: input) Serial data input Data transfer is active while the CE pin is high level. Data transfer proceeds in LSB to first order. Data input is synchronized with the rising edge of the clock. Data output is synchronized with the falling edge of the clock.
Notes: Do not write command or other data to the serial data input pin while the LSI is writing data. The serial data output pin is in the high impedance state during data input. 2-1 Address and data transfer procedures The command address is assigned to the lowest seven bits of the address. The most significant bit (AD7) is used to specify write or read. The address can only be written. It cannot be read. Data transfer proceeds in LSB to first order. Address input and data I/O are valid while the CE pin (pin 43) is high level. Supply the serial data input clock to the CL pin (pin 44). The LSI reads and writes data in synchronization with the rising edge of the serial clock signal.
No. 5684-17/21
LC74201E * Writing data Data input is via the DI pin (pin 46). The lowest seven bits give the address. The top bit is 0. The command address is assigned to the lowest seven bits.
Write the data after specifying the address.
* Reading data Data output is via the DO pin (pin 45). The lowest seven bits give the address. The top bit is 0. The command address is assigned to the lowest seven bits.
Read the data after specifying the address.
No. 5684-18/21
LC74201E 2-2 Timing characteristics at Ta = +25C, DVDD1 = 3.7 V
Parameter Symbol twH2 twL2 tr3 tf3 tsDI14 thDI14 tsCE1 thCE1 tWT1 tWT2 tWRT2 tREAD2 tPLH1 tPHL2 Conditions CL pin high level pulse width CL pin low level pulse width CL pin CL pin DI CL pin CL CL pin CE pin CE pin Serial data read- in time Serial transfer restart time DI and CL pins (1 word = 8 bits) DI and CL pins (1 word = 8 bits) Serial data output high propagation time Serial data output low propagation time Ratings min 180 180 - - 25 25 25 25 180 360 1.6 1.6 - - max - - 50 50 - - - - - - - - 150 55 Unit ns ns ns ns ns ns ns ns ns ns s s ns ns
Minimum input pulse width Clock rising time Clock falling time Data setup time Data hold time CE setup time CE hold time Data read-in time Data restart time Single to word write time Single to word read time Data output propagation time
Note: The DO output pin uses N-channel open-drain output. The standard values for tpLH2 and tpHL2 are for an output load capacitance of 50 pF, an external pull-up resistor of 2.7 k, and an output level of 5 V
No. 5684-19/21
LC74201E * Serial data write timing
* Serial data read timing
Note: Data input is invalid during data output.
No. 5684-20/21
LC74201E External DRAM Mappings 4 M bit configuration
4 M + 1 M bit configuration
Functions Available with the Two External DRAM Capacities
Item PAL high to resolution still image High to resolution still image switching Video bit buffer capacity User area capacity 4 M bits 4 M + 1 M bits Top and bottom 48 lines of image suppressed Full image display Display blanked 52 kB 8 kB (4 sectors) Image overwritten from top of display 63.5 kB 22 kB (11 sectors)
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5684-21/21

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